The Rise of RISC-V

Introduction

The golden age of computer architecture that we are living in to borrow from David Patterson, also includes the Open ISA, segueing away from the days of proprietary and licensed ISA (x86 and ARM).

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What is ISA?

A quick gist of the ISA

An Instruction Set Architecture (ISA) is an abstract model of a computer that defines how software controls the CPU. The fundamental instruction sets that the Processor understands in the lowest level, in order to execute higher level programming languages. ISA typically are arithmetic, logical operations and handle data movement across memory and processor, and across memories and registers.

History and Evolution of ISA

The evolution of ISAs has largely been characterized by compute requirements various segment specific KPIs:

Complex Instruction Set Computer (CISC): Early ISAs, like Intel's x86, were designed to have a large and complex set of instructions, often performing multiple operations with a single instruction. The idea was to reduce the number of instructions needed for a program, simplifying compilers. However, this often led to complex hardware designs and variable instruction execution times, and are expensive in terms of clock cycles.



Reduced Instruction Set Computer (RISC): Pioneered in the 1980s, RISC architectures aimed for a smaller, simpler set of instructions, each taking roughly the same amount of time to execute. While this might require more instructions for a given task, it simplifies the hardware, enabling faster clock speeds and more efficient pipelining (executing multiple instructions concurrently). In general,, RISC is also a power efficient architecture. This system provides a means for latency critical designs. ARM is a prominent example of a RISC ISA.

RISC-V: is a specialised case of RISC ISA, where the ISA alone (not the HW implementation in general) is open.


DSP, Specialized IPs & Microprocessors: These continue as a niche segment for limited nonetheless specialized instruction set.

The trend has generally moved towards RISC principles due to their efficiency and scalability, especially in mobile and embedded systems. While CISC, has been well adopted in General Compute and High Performance compute, as the software evolved around x86 based architecture.

ARM vs. x86 vs. RISC-V

A comparison of the three dominant and emerging ISAs:

Feature	x86	ARM	RISC-V
Philosophy	CISC (Complex Instruction Set Computer)	RISC (Reduced Instruction Set Computer)	RISC (Reduced Instruction Set Computer)
Ownership	Proprietary (Intel, AMD)	Proprietary (Arm Holdings licenses its ISA)	Open Standard (governed by RISC-V International)
Licensing	Closed, high licensing fees	Licensing fees required	Royalty-free, open-source specification
Customization	Limited, vendor-controlled	Limited, vendor-controlled	Highly customizable and extensible via extensions
Ecosystem	Mature, dominant in PCs, servers, workstations	Mature, dominant in mobile, embedded, growing in servers	Rapidly growing, strong community support
Applications	Desktops, laptops, servers, data centers	Smartphones, tablets, IoT, automotive, embedded, servers	IoT, embedded, AI/ML, automotive, HPC, data centers
Security	Proprietary, potential for hidden backdoors	Proprietary	Open for scrutiny, enhanced transparency
Innovation	Driven by large corporations	Driven by Arm Holdings and licensees	Community-driven, fosters broad innovation

Key Differentiator: The fundamental difference lies in their business models. x86 and ARM are proprietary, meaning companies must pay licensing fees to use their technology.

RISC-V, is an open standard, allowing anyone to design, manufacture, and sell RISC-V chips without paying royalties.

This does not imply that the HW Implementation is free, which also is available from some companies and organisations.

Current Focus and Status of RISC-V

RISC-V is experiencing rapid growth and adoption across various segments from: IoT, Embedded, High Performance Compute, Automotive, RAN. Some evaluation platforms for PCs, Edge based platforms are also available.

Standardization: RISC-V International, the governing body, is actively working on ratifying and publishing new specifications and extensions to mature the ecosystem and ensure compatibility.This includes profiles that define standard collections of instructions for different application areas.

Ecosystem Development: A significant effort is being put into developing a robust software ecosystem, including operating system support (Linux, Android, Zephyr, etc.), compilers (LLVM/Clang), development tools, and libraries. Unofficial port of MS Windows is also under evaluation.

Performance and Scalability: While initially popular for low-power embedded applications, RISC-V is increasingly targeting higher-performance segments like AI/ML accelerators, high-performance computing (HPC), and data centers. Many new AI IPs are available as RISC-V.

RISC-V is slowly gaining prominence in the Radio Access Network Telco segment .

Security: The open nature promotes better security. security features are being actively integrated and reviewed, allowing for transparent design and verification.

RISC-V Market Segments, Volumes, and Projections

The RISC-V market is generally categorized by application or end-user industry, as well as by product type (e.g., MCU, MPU, SoC). The overall market size, according to various reports, was around USD 1.44 billion in 2024 and is projected for substantial growth.

KPI	Value / Range	Notes
2024 Market Size	USD 1.35B – USD 1.5B	Most reports converge around USD 1.44B
Projected Market Size (2030–2034)	USD 2.5B (2030) – USD 17.87B (2034)	Several forecasts estimate USD 11B–17B by 2032–2034
CAGR (2025–2032/2034)	21.4% – 33.1%	One report projects 29.66% CAGR for overall RISC-V tech market (2025–2032)
RISC-V CPU Core Unit Shipments	3.0B (2023) → 62.4B (2025)	~20x increase in just two years, signaling rapid ecosystem adoption

Key Segments and Projections:

An overview of the key segments of RISC-V based products -

Segment (by Application/End-User)	Estimated Percentage/Share (2024)	Projected Growth/CAGR	Notes
IoT Devices	35% of revenue share (largest)	Strong growth (leading)	Driven by increasing demand for smart, connected solutions, energy efficiency, and customization in healthcare, manufacturing, and transportation. Low-cost, low-power 32-bit RISC-V cores are highly suitable here.
Consumer Electronics	~24% of total revenue share	High growth	Includes smartphones (companion cores, potentially main), smart TVs, wearables, home automation. Driven by demand for advanced, cost-effective, and customizable solutions.
Automotive and Transportation	Rapid growth	~36.77% CAGR	Advancements in EVs, autonomous driving, and smart mobility. Strong demand for customizable, secure, and reliable chips for ADAS and in-cabin smart technology. Omdia projects 66% annual growth.
Industrial	Expected to be largest by volume	Very high (e.g., 16.7B cores by 2025)	Driven by automation, industrial IoT, and need for specialized, robust processors. Omdia expects it to be 46% of sales by 2030.
AI/Machine Learning (AI SoC)	USD 542 million (2024)	~15.0% CAGR (AI SoC), 50% annual growth for RISC-V in AI until 2030	RISC-V's extensibility allows for custom instructions and accelerators, making it ideal for AI inference and training, especially at the edge. Major tech companies are investing in RISC-V for AI data centers.
Computing and Storage	Significant growth	High growth	Includes data centers, servers, and potentially desktops/laptops (especially for specialized workloads). High-performance 64-bit RISC-V cores are increasingly targeting this space.
Communication Infrastructure (Telecom)	Fast growth	~209% CAGR (cores)	Includes 5G equipment. Demand for efficient and flexible processors in networking, RAN, Small Cells, equipment.
Medical	Growing		Applications in medical devices and healthcare technology.
Aerospace and Military	Growing		Driven by security, reliability, and domestic control over technology.

Note: Percentages may refer to revenue or unit share, and specific figures can vary slightly between different market research reports due to varying methodologies and forecast periods. The data presented here is based on recent projections from 2024-2025 reports.Numbers generated by Google Gemini in table above.

The following table reflects the high-growth environment for RISC-V companies:

Company Type/Focus Area	Current Revenue Status (General)	Projected CAGR (Inferred from Market)	Notes
RISC-V IP Vendors	Growing, typically in the tens to hundreds of millions USD	High (e.g., >30-40%)	Companies like SiFive, Andes Technology, Codasip, Nuclei System Technology. Their revenue is directly tied to the adoption of RISC-V designs. RISC-V IP revenues surged to $156M in 2023 with 39.5% CAGR through 2030.
RISC-V Chip Designers/SoC Companies	Revenue tied to specific product sales (e.g., AI accelerators, embedded chips)	Very High (aligned with segment growth, e.g., automotive 36.77% CAGR)	Companies like Esperanto Technologies, Ventana Micro Systems, StarFive. They sell finished chips or systems incorporating RISC-V.
Major Tech Companies (using RISC-V internally)	Billions in overall revenue, RISC-V contribution growing	Significant (as RISC-V becomes core to new products)	Google, NVIDIA, Qualcomm, Intel, Meta, Western Digital. Their RISC-V "revenue" is often cost savings or enhanced product capabilities, rather than a direct line item.
EDA Tool & Ecosystem Providers (supporting RISC-V)	Varied, often established large companies	Moderate to High (aligned with design starts)	Companies providing design tools, verification services, software development kits (e.g., Synopsys, Cadence, Mentor Graphics, Imperas). Growth driven by increased RISC-V design activity.

Benefits and Risks

Benefits

• Open Standard and Royalty-Free



• Customization and Extensibility

• Transparency and Security

• Reduced Vendor Lock-in

• Cost-Effectiveness

• Long-Term Availability

• Open Source Community-Driven Innovation

  
  

Risks

• Ecosystem Maturity

• Fragmentation Concerns

• Lack of Centralized Support

• Performance for High-End Applications

Europe and Germany Focus

Europe, and specifically Germany, are actively embracing RISC-V as a strategic imperative for achieving digital sovereignty and fostering regional innovation

Digital Autonomy: Europe views RISC-V as a crucial technology to reduce reliance on non-European proprietary architectures (x86 and ARM) and build indigenous semiconductor capabilities.



EuroHPC JU (European High-Performance Computing Joint Undertaking): This initiative is heavily funding projects like DARE (Digital Autonomy with RISC-V in Europe), which aims to develop cutting-edge HPC hardware and software based on RISC-V.

European Joint Ventures and Companies:

Quintauris: A prominent European joint venture involving Bosch, Infineon, Nordic Semiconductor, NXP, STMicroelectronics, and Qualcomm, focusing on automotive RISC-V chips.



Codasip: A European company (headquartered in Munich, Germany) that designs high-end RISC-V processor IP and is involved in EU-funded projects like DARE.



Barcelona Supercomputing Center (BSC): A key coordinator of the DARE project and a significant contributor to RISC-V research and development in Europe.

Other European players include Semidynamics (Spain), VyperCore (UK), and Scaleway (France), offering RISC-V servers in the cloud.



Research and Academia: European universities and research institutions are actively conducting research on RISC-V, contributing to its technical development and training the next generation of engineers.



RISC-V Summit Europe: An annual event that brings together European stakeholders from industry, government, research, and academia to discuss and advance RISC-V adoption. The 2025 summit is taking place in Paris, highlighting Europe's commitment.



AI Factories: The EuroHPC JU is also investing in "AI Factories" across Europe, including in Germany, which will leverage EuroHPC supercomputing facilities and aim to support the growth of a competitive AI ecosystem, potentially incorporating RISC-V.



Germany's strong industrial base, particularly in automotive and industrial automation, makes it a fertile ground for RISC-V adoption. Fraunhofer institutes, like Fraunhofer IIS, are actively involved in research and development around RISC-V for various applications

Next Steps for RISC-V

Top 5 Strategic Imperatives over the next decade

1. Software Maturity – parity with ARM in toolchains, middleware, and OS support.

2. Commercial Core Offerings – high-performance, validated IP from trusted vendors.

3. Security Architecture – mainstream deployment of TEEs, side-channel hardening.

4. Ecosystem Governance – prevent fragmentation via strict profile enforcement.

5. Talent and Toolchain – open-source silicon design tools and skilled engineers.

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